1. Field of the Invention
The present invention is in the field of integrated circuits, particularly semiconductor memory circuits, and is more particularly directed to the disabling of edge transition detection pulses during flash clear of the memory array.
2. Description of the Prior Art
Semiconductor memories, such as random access memories (RAMs) and read-only memories (ROMs) are typically designed to operate in response to input signals in either a clocked or an asynchronous (unclocked) manner. One type of integrated circuit which operates primarily on asynchronous signals is a static random-access memory (SRAM). SRAMs are designed to receive address values at address terminals, and to statically provide read or write access to memory cells corresponding to the value of the address applied thereto, without relying on a clock signal indicating that the value at its address terminals is valid.
Many modern SRAMs now include edge transition detection (ETD) circuits such as address transition detection (ATD) circuitry and other timing and control circuits that provide the SRAM device with performance benefits of internal dynamic operation. An ETD circuit detects transitions within the device and generates internal signals or "pulses" responsive to detecting such transitions.
For example, the use of an ATD circuit allows the SRAM circuit to perform certain internal operations, such as precharging bitlines or deselecting sense amplifiers, after detection of the address transition, but before the decoders access the desired cell. Upon presentation of a new memory address to the SRAM, the transitions at the address terminal cause the ATD circuit to enable the necessary functions of the SRAM to access the memory cells selected by the new memory address. An example of an ATD circuit used in SRAMs is described in U.S. Pat. No. 5,124,584, issued on Jun. 23, 1993, assigned to SGS-Thomson Microelectronics and herein incorporated by this reference.
The design of SRAM circuits to respond to unclocked signals increases the sensitivity of the device to noise or other spurious signals, thereby causing performance degradation, decreased reliability, or other serious problems. Consider, for example, an SRAM device incorporating a flash clear cycle in its architecture. Flash clear is of particular utility in SRAMS used in computer cache memories. Also known as flash write, flash clear is used to write to all memory cells (or selected cells) simultaneously. A computer cache memory duplicates selected data from the main memory allowing a computer central processing unit (CPU) faster access to that data than can be obtained from a system's main memory. The protocol for selection of the data to be duplicated is critical to the effective operation of the cache. The flash clear operation can be used to clear all resident data from SRAMS of the cache, such as in tag arrays or data storage, where a selection protocol requires such an operation.
Initiation of a flash clear cycle results in relatively large currents on an SRAM. Current transients may be in the range of amperes, bordering on capacity limitations of the devices involved. If an ATD circuit or other timing and control circuit generates an edge transition detection pulse, a serious problem may occur. For example, if an address or clock changes state, an edge transition detection pulse (ETD) is generated. This pulse is frequently used to short bitline true to bitline complement and precharge both to V.sub.cc (or V.sub.cc -V.sub.TN) in many devices. If this occurs during a flash clear, a crowbar condition is created on every column cleared, generating "beyond capacity" crowbar currents throughout the device.
Conventional system designs combat these problems by making any address or clock change illegal during the flash clear. This can be rather restrictive in the system environment, however, and does not reliably prevent oscillations or noise from initiating an internal edge transition detection pulse. In addition, the flash clear cycle can cause huge current transients (both AC and DC). Noise induced by the transients can cause temporary input transitions (internal to the part) even when the signal is static external to the device. The false transition, which can generate a false ETD pulse, causing ever larger current transients, more noise, more false transitions, resulting in oscillations disruptive to the proper functioning of the SRAM device.
Therefore, it would be desirable to have a method and system for temporarily disabling edge transition detection circuitry during the flash clear cycle to protect the device from transient currents, noise and other harmful effects.